1. Field of the Invention
The present invention relates to a computer system and a method for controlling a processor thereof. More particularly, the present invention relates to a computer system and a method for controlling a processor to avoid an unpredictable behavior during adjusting the operating condition of the processor.
2. Description of the Related Art
When a processor in a computer system has to change to another operating mode, generally the operating condition of the processor has to be adjusted accordingly, and the task of adjusting the operating condition is usually done by another device. For instance, when a modern processor gets no task to do, it usually enters a standby mode, where it turns off most of its circuit except a small portion to wait for external wakeup events to bring it back to a consistent operating mode. When the processor prepares to enter the standby mode, the processor communicates with a processor management unit (PMU) for its new operating condition including supply voltage and/or operating frequency, and the PMU starts the adjustment of the operating condition after the processor enters the standby mode.
Most of the modern processors have a standby notification signal going out to the PMU in order to notify the PMU to start adjusting the operating condition, but there is no signal going from the PMU to the processor to notify the processor that the adjustment of the operating condition is complete. As a result, if a wakeup event, such as an interrupt, arrives when the processor is in the standby mode and the PMU is still adjusting the operating condition, the processor may wakeup prematurely and be forced to work with inconsistent operating condition. Unpredictable behaviours such as race condition and instability might happen.
In order to prevent such unpredictable behaviours, a conventional solution is using an ad hoc system level logic circuit outside the processor for blocking wakeup events during the adjustment of the operating condition. However, there are many sources which can send wakeup events to the processor, thus the system level logic circuit has to block these wakeup events in different ways according to the different sources. In addition, the system level logic circuit has to detect whether the adjustment of the operating condition is complete. As a result, the complexity of the system level logic circuit is high. Besides, the design of the system level logic circuit is also limited to the interfaces of the existing functions provided by the processor and the PMU. Consequently, the flexibility of blocking wakeup events is also limited. Without an integrated mechanism to solve the problem of premature awakening, unpredictable behaviours might happen and both the stability and the reliability of the entire computer system will be affected.